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The-OpenROAD-Project/OpenLane

★ 1,828 · Python · Apache-2.0 · updated Mar 2026

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

OpenLane is an RTL-to-GDSII flow that chains together Yosys, OpenROAD, Magic, KLayout, and Netgen into a single Docker-based pipeline targeting the SkyWater 130nm PDK. It was the go-to open-source ASIC flow for Google MPW shuttle participants from 2020–2023. It is now in maintenance mode — the project itself says don't use it for new designs.

Proven at tape-out: hundreds of real chips went through this flow on Efabless shuttles, so the Tcl scripts and configuration knobs are battle-tested against actual silicon. The Docker packaging solves the dependency nightmare of stitching together EDA tools that rarely agree on shared libraries. Configuration is a single JSON/Tcl file per design, which is a reasonable interface given the underlying complexity. The regression suite includes benchmark CSVs with real timing/area numbers, not just 'it ran without errors.'

Officially deprecated — the README opens with 'not recommended for new projects.' If you start a design here you are immediately accumulating technical debt. The flow is almost entirely Tcl scripts gluing together external tools; when something goes wrong mid-run you are debugging Tcl stack traces across five different tool boundaries. No support beyond SKY130 in any practical sense — other PDKs exist in forks but are community-maintained at best. The successor (LibreLane) exists and is actively developed, so any time spent learning OpenLane-specific quirks is time not spent on the thing that will matter next year.

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