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ai-hpc/ai-hardware-engineer-roadmap
Master AI inference, AI agent harness systems, and hardware engineering — then design a physical AI chip. That is the goal.
A structured self-study curriculum for engineers who want to go from software to silicon — specifically, designing a physical AI chip that combines Jetson-class compute, ESP32-class wireless, and an agent runtime on one SoC. The roadmap is organized into five phases across three pillars: inference engineering, agent harness systems, and embedded/hardware. It targets people who already code and want to add depth in at least one hardware direction.
The co-design framing is genuinely useful — showing how inference workload shapes the NPU spec, which shapes the memory hierarchy, rather than treating each as an isolated study track. The Phase 5 inference lecture series (Qwen roofline through batched GEMM) has concrete, technical content that goes well beyond most self-study resources. The reference projects are real: genie-ai-runtime ships 38 tok/s on Orin Nano and the numbers are cited, not estimated. The completion standard ('build something, measure it, explain the tradeoff') is written into the curriculum explicitly, which keeps it from being a pure reading list.
217 stars for something this ambitious suggests few people have actually completed it — there's no community validation that the curriculum hangs together in practice. The scope is genuinely enormous: ASIC tape-out, FCC compliance, multi-GPU tensor parallelism, and Zigbee in one roadmap. A realistic timeline is never given, and most people who start will stall somewhere in Phase 2 before touching the interesting parts. The agent harness pillar (Track B) leans heavily on LangGraph and third-party SDKs rather than teaching the underlying runtime concepts, so if those APIs change the curriculum dates fast.