// the find
f9micro/f9-kernel
An efficient and secure microkernel built for ARM Cortex-M cores, inspired by L4
F9 is an L4-family microkernel targeting ARM Cortex-M4/M4F, designed for hard real-time embedded systems where you need hardware MPU isolation without the weight of a full RTOS. It's for developers building safety-conscious firmware on STM32 who want microkernel architecture—address spaces, IPC, proper memory protection—at the resource level of an MCU.
O(1) priority bitmap scheduler with preemption-threshold scheduling is a genuine engineering choice, not marketing—PTS reduces context switches in critical sections without disabling interrupts, which is a real win for determinism. The POSIX PSE51 layer is implemented entirely in userspace on top of the notification primitives, meaning it adds zero kernel complexity and you can ignore it if you don't need it. KProbes support on a microcontroller is unusual and genuinely useful for debugging production firmware without recompilation. QEMU support with automated regression tests via CI means you can develop and test without hardware.
Hard-locked to ARM Cortex-M4/M4F with STM32 peripherals—the MPU has only 8 regions, which is a hard architectural ceiling that will bite you if your application has more than a handful of isolated components. The POSIX timer support is explicitly partial ('limited functionality' per the README), so anything timing-sensitive that reaches for timer_create will hit a wall. No dynamic memory allocation in the kernel—flexible pages must be power-of-2 aligned, which makes fragmentation a real design concern for anything beyond simple task decompositions. The project has 761 stars and 153 forks but the last push was March 2026; the community is small and production war stories are essentially nonexistent, so you're largely on your own if you hit an edge case in IPC or the MPU configuration.