// the find
skyzh/RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
A RV32I simulator written in C++ as a computer architecture course project, progressing from sequential through pipelined to out-of-order execution with Tomasulo + speculation. The progression across branches — seq → feedforward → pipeline → out-of-order — makes it a decent study aid for anyone working through CA:AQA Chapter 3. Not a tool you'd use in production; it's educational software with a well-documented design process.
The multi-branch structure lets you compare implementations directly — the same ISA, different microarchitecture decisions, all in one repo. The two-level adaptive branch predictor is actually implemented, not stubbed. There's a PDF project report (in Chinese) that explains the non-obvious design choices, like handling jalr and memory hazards in Tomasulo without a full circuit design. GTest is wired up and the CI runs against a suite of real programs (qsort, queens, hanoi) not just toy opcodes.
Dead since 2020 and the Travis CI badges are all broken, so you can't verify builds without setting up a local toolchain. Only RV32I — no M extension, no CSRs, no privilege levels, so it won't run anything beyond simple academic programs. The visualization requires recompiling against main_presentation.cpp rather than being a runtime flag, which is annoying. Codebase is a single student project with no contribution guidelines and minimal comments in the source, so if you're trying to extend it rather than just read it, you're mostly on your own.