// the find
LaurieWired/tailslayer
Library for reducing tail latency in RAM reads
Tailslayer is a C++ template library that hides DRAM refresh-induced read latency spikes by replicating a value across multiple independent DRAM channels and racing hedged reads across them, taking whichever replica returns first. It's aimed at people building extremely latency-sensitive systems (HFT, real-time control loops) who care about tail latency more than average latency or memory footprint.
The core idea is legitimately clever: DRAM channels don't refresh in lockstep, so probabilistically at least one replica is never mid-refresh when you read it, which is a real hardware-level fix rather than a software workaround. It ships the `discovery/trefi_probe.c` and benchmark harness used to actually characterize the refresh spikes on AMD/Intel/Graviton, so the claims aren't just asserted, they're measurable. The signal/work callback design with `always_inline` template parameters means there's no virtual dispatch or function pointer overhead sitting between the hedge and the hot path.
It only supports two channels in the actual library; N-way replication exists solely in the benchmark code, so anyone wanting the full technique has to port that logic in themselves. The channel scrambling offsets are explicitly called out as undocumented and reverse-engineered, meaning correctness depends on CPU-vendor internals that could silently shift with a new stepping or microcode update and there's no fallback detection for that. Each replica spins on its own pinned core waiting for the signal function, so this trades cores and power for latency, and the README doesn't discuss how it behaves under normal (non-`chrt -f 99`, non-isolated-core) scheduling. There's no test suite in the tree, just the example and benchmark, so regressions in the offset/scrambling logic would only show up as a performance change, not a failing test.